SCI Wonder Chip Information		R. Grieb	4/15/2016

Note:   This information is based on the TOM code disassembly and 
some testing done with a Z80 ICE and a TOM unit, and may contain errors.

	The Sequential Wonder chip (I607) generates sequential addresses for up to four
waveforms and feeds them, one at a time, to the attached EPROM or ROM memory chips.
So it has four counters which can be loaded by the Z80, and either incremented
or decremented (for reversing the sound) at a programmable rate (based on the pitch
of that sound).  Only three address lines are used, so there are only eight "registers"
that can be written to.  Actually, there is a set of registers for each of the four
channels, but only one set is selected at a time.

   Here is some information about how the eight addresses are used inside the chip.
   
Address 0:
	D7		Setting this bit causes the counter to decrement, playing the sound backwards
			Not sure if this is one bit for all channels (probably) or one for each
	D6  	Unused?
	D5-4    Selects which channel (0-3) we are accessing
	D3-0	These bits map directly to the volume control pins which set the DAC reference voltage,
			so there must be a register loaded from these bits for each channel
			
Address 1:

	D7		Unused?
	D6-0	7-bit complemented sample period, so 0x7F gives a sample period of 1, 0x7E gives 2, etc
			Maybe this value is used to load a 7-bit counter that increments, and is reloaded when it wraps?
			There are four of these sample rate counters, each with its own rate, so there must be four copies
			of these bits, selected by D5-4 in address 0.  The 500 KHz clock is used to increment the sample
			period counters, so each count is 2 uSec long.
			
Address 2:

	D7-0	A8-A1 of the sample starting address (or the ending address if playing backwards)
			Since the Wonder chip must address a 17-bit address space, it seems the designer decided to save
			logic by always setting A0 to 1 when this register is written, and providing CPU access to only the 
			upper 16 bits using two register addresses.   CMOS gate array chips were available in specific sizes, 
			like 400 gates or 700 gates.   If the gate count could be reduced to fit into a smaller chip, the cost 
			would drop.
			
Address 3:

	D7-0	A16-A9 of the sample starting address (or the ending address if playing backwards)
	
Address 4:

	D7-0	Bits 8-1 of the sample byte count.  Not sure what value bit 0 was set to.
			
Address 5:

	D7-0	Bits 16-9 of the sample byte count.   Writing to this address also seems to start the 
			sample playing.
	
Address 6:	Written to once in the code with a value of 0x11. I have no idea what this is for.

Address 7:	

	D7 		Seems to inhibit playing samples.   The code writes 0x80 then 0x40.   It seems that
			this may be resetting the Wonder chip.   Perhaps writing 0x80 sets a global reset signal,
			and writing 0x40 clears that signal.
			
	D6-0	Unused?
	
	
Additional information:

	It seems that not all bits of the starting address low register can be written.  Address values in the sound
EPROMs always have 0 as the low nibble.  Probably those bits of the register are always reset whenever it is written.
That would have saved a few gates.   I tried writing ones to those bits in a cartridge that I was creating and got
strange results, so probably they are always cleared, regardless of the data bus value.  This just means sound waveforms
must start on 32-byte boundaries in the EPROM.

	The TOM code that reads the wave EPROM headers writes 0's to addresses 4 and 5 in sequence to increment the address by two.
It seems the only way to increment the address may be to play a sample, so they set the sample length to 0x0000 by writing to
addresses 4 and 5.   Writing to address 5 also starts the sample playing, from the current address, but since the count has
been set to 0, we just get two samples and then it shuts off again.  This is how the cartridge headers are read.  The header data
nibbles are placed on every other address, so probably there is no way to increment the address by just one.  So it seems
possible that giving the Z80 a way to read data from the cartridges was not part of the Wonder chip design, but they figured out
after the chip was made how to make it work.